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may 2010 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator fan5355 1a / 0.8a, 3mhz digitally programmable regulator features ? 93% efficiency at 3mhz ? 800ma or 1a output current ? i 2 c?-compatible interface up to 3.4mbps ? 6-bit v out programmable from 0.75v to 1.975v ? 2.7v to 5.5v input voltage range ? 3mhz fixed-frequency operation ? excellent load and line transient response ? small size, 1 h inductor solution ? 2% pwm dc voltage accuracy ? 35ns minimum on-time ? high-efficiency, low-ripple, light-load pfm ? smooth transition between pwm and pfm ? 37 a operating pfm quiescent current ? pin-selectable or i 2 c? programmable output voltage ? on-the-fly external clock synchronization ? 10-lead mlp (3 x 3mm) or 12-bump csp packages applications ? cell phones, smart phones ? 3g, wifi ? , wimax?, and wibro ? data cards ? netbooks ? , ultra-mobile pcs ? smartreflex?-compliant power supply ? split supply dsps and p solutions omap?, xscale? ? mobile graphic processors (nvidia ? , ati) ? lpddr2 and memory modules description the fan5355 device is a high-frequency, ultra-fast transient response, synchronous step-down dc-dc converter optimized for low-power applications using small, low-cost inductors and capacitors. the fan5355 supports up to 800ma or 1a load current. the device is ideal for mobile phones and similar portable applications powered by a single-cell lithium-ion battery. with an output-voltage range adjustable via i 2 c? interface from 0.75v to 1.975v, the device supports low-voltage dsps and processors, core power supplies, and memory modules in smart phones, pdas, and handheld computers. the fan5355 operates at 3mhz (nominal) fixed switching frequency using either its internal oscillator or external sync frequency. during light-load conditions, the regulator includes a pfm mode to enhance light-load efficiency. the regulator transitions smoothly between pwm and pfm modes with no glitches on v out . in hardware shutdown, the current consumption is reduced to less than 200na. the serial interface is compatible with fast/standard and high-speed mode i 2 c specifications, allowing transfers up to 3.4mbps. this interface is used for dynamic voltage scaling with 12.5mv voltage steps for reprogramming the mode of operation (pfm or forced pwm), or to disable/enable the output voltage. the chip's advanced protection features include short-circuit protection and current and temperature limits. during a sustained over-current event, the ic shuts down and restarts after a delay to reduce average power dissipation into a fault. during startup, the ic controls the output slew rate to minimize input current and output overshoot at the end of soft start. the ic maintains a consistent soft-start ramp, regardless of output load during startup. the fan5355 is available in 10-lead mlp (3x3mm) and 12-bump csp packages. i 2 c is a trademark of philips corporation. wi-fi? is a registered trademark of wi-fi alliance corporation. wimax? is a trademark of wimax forum corporation. wibro? is a registered trademark of telecommunications technology association. netbooks? is a registered trademark of netbooks, inc. smartreflex and omap are trademarks of texas instruments. xscale is a trademark of intel corporation. nvidia is a registered trademark of nvidia corporation.
? 2008 fairchild semiconductor corporation 2 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator ordering information order number (1) option slave address lsb output current v out programming power-up defaults package a1 a0 ma min. max. vsel0 vsel1 FAN5355UC00X 00 0 0 800 0.7500 1.5375 1.05 1.35 wlcsp-12, 2.23x1.46mm fan5355mp00x 00 0 0 800 0.7500 1.5375 1.05 1.35 mlp-10, 3x3mm fan5355uc02x 02 1 0 800 0.7500 1.4375 (2) 1.05 1.20 wlcsp-12, 2.23x1.46mm fan5355uc03x 03 0 0 1000 0.7500 1.5375 1.00 1.20 wlcsp-12, 2.23x1.46mm fan5355uc06x 06 0 0 1000 1.1875 1.9750 1.80 1.80 wlcsp-12, 2.23x1.46mm notes: 1. the ?x? designator specifies tape and reel packaging. 2. v out is limited to the maximum voltage for all vsel codes greater than the maximum v out listed. typical application sw q1 q2 modulator pgnd pvin c out vout l out vout c in en vsel sync agnd sda scl avin vin vccio figure 1. typical application component description vendor parameter min. typ. max. units l1 (l out ) 1 h nominal murata lqm31p or fdk mipsa2520 l (3) 0.7 1.0 1.2 h dcr (series r) 100 m c out 0603 (1. 6x0.8x0.8) 10 f x5r or better murata or equivalent grm188r60g106me47d c (4) 5.6 10.0 12.0 f c in 0603 (1.6x0.8x0.8) 4.7 f x5r or better murata or equivalent grm188r60j475ke19d c (4) 3.0 4.7 5.6 f table 1. recommended external components notes: 3. minimum l incorporates tolerance, temperature, and partial saturation effects (l decreases with increasing current). 4. minimum c is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects.
? 2008 fairchild semiconductor corporation 3 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator pin configuration top view bottom view top view figure 2. wlcsp-12, 2.23x1.46mm figure 3. mlp10, 3x3mm pin definitions pin # name (5) description wlcsp mlp a1, b1 9 pgnd power gnd . power return for gate drive and power transistors. connect to agnd on pcb. the connection from this pin to the bottom of c in should be as short as possible. a2 10 sw switching node . connect to output inductor. a3 1 pvin power input voltage . connect to input power source. the connection from this pin to c in should be as short as possible. b2 n/a sync sync . when toggling and sync_en bit is high, the regulator synchronizes to the frequency on this pin. in pwm mode, when this pin is statically low or statically high, or when its frequency is outside of the specified capture range, the regulator?s frequency is controlled by its internal 3mhz clock. b3 2 avin analog input voltage . connect to input power source as close as possible to the input bypass capacitor. c1 8, pad agnd analog gnd . this is the signal ground reference for the ic. all voltage levels are measured with respect to this pin. c2 7 en enable . when this pin is high, the circuit is enabled. when low, quiescent current is minimized. this pin should not be left floating. c3 3 sda sda . i 2 c interface serial data. d1 6 vout output voltage monitor . tie this pin to the output voltage. this is a signal input pin to the control circuit and does not carry dc current. d2 5 vsel voltage select . when high, v out is set by vsel1. when low, v out is set by vsel0. this behavior can be overridden through i 2 c register settings. this pin should not be left floating. d3 4 scl scl . i 2 c interface serial clock. note: 5. all logic inputs (sda, scl, sync, en, and vsel) are high impedance and should not be left floating. for minimum quiescent power consumption, tie unused logic inputs to avin or agnd. if i 2 c control is unused, tie sda and scl to avin.
? 2008 fairchild semiconductor corporation 4 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v cc avin, sw, pvin pins -0.3 6.5 v other pins -0.3 avin + 0.3 (6) v esd electrostatic discharge protection level human body model per jesd22-a114 3.5 kv charged device model per jesd22-c101 1.5 kv t j junction temperature ?40 +150 c t stg storage temperature ?65 +150 c t l lead soldering temperature, 10 seconds +260 c note: 6. lesser of 6.5v or avin+0.3v. recommended operating conditions the recommended operating conditions table defines the condi tions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v in supply voltage 2.7 5.5 v f frequency range 2.7 3.3 mhz v ccio sda and scl voltage swing (7) 2.5 v t a ambient temperature ?40 +85 c t j junction temperature ?40 +125 c note: 7. the i 2 c interface operates with t hd;dat = 0 as long as the pull-up voltage for sda and scl is less than 2.5v. if voltage swings greater than 2.5v are required (for example if the i 2 c bus is pulled up to v in ), the minimum t hd;dat must be increased to 80ns. most i 2 c masters change sda near the midpoint between the falling and rising edges of scl, which provides ample t hd;dat . dissipation ratings (8) package r ja (9) power rating at t a 25c derating factor > t a = 25oc molded leadless package (mlp) 49oc/w 2050mw 21mw/oc wafer-level chip-scale package (wlcsp) 110oc/w 900mw 9mw/oc notes: 8. maximum power dissipation is a function of t j(max) , ja , and t a . the maximum allowable power dissipation at any allowable ambient temperature is p d = [t j(max) - t a ] / ja . 9. this thermal data is measured with high-k board (f our-layer board according to jesd51-7 jedec standard).
? 2008 fairchild semiconductor corporation 5 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator electrical specifications v in = 3.6v, en = v in , vsel = v in , sync = gnd, vsel0(6) bit = 1, control2[4:3] = 00. t a = -40c to +85c, unless otherwise noted. typical values are at t a = 25c. circuit and components according to figure 1. symbol parameter conditions min. typ. max. units power supplies v in input voltage range 2.7 5.5 v i q quiescent current i o = 0ma, pfm mode 37 50 a i o = 0ma, 3mhz pwm mode 4.8 ma i sd shutdown supply current en = gnd 0.1 2.0 a en = v in , en_dcdc bit = 0, sda = scl = v in 0.1 2.0 v uvlo under-voltage lockout threshold v in rising 2.40 2.60 v v in falling 2.00 2.15 2.30 v v uvhyst under-voltage lockout hysteresis 200 250 300 mv enable, vsel, sda, scl, sync v ih high-level input voltage 1.2 v v il low-level input voltage 0.4 v i in input bias current input tied to gnd or v in 0.01 1.00 a power switch and protection r ds(on)p p-channel mosfet on resistance v in = 3.6v, csp package 145 m ? v in = 3.6v, mlp package 165 v in = 2.7v, mlp package 200 i lkgp p-channel leakage current v ds = 6v 1 a r ds(on)n n-channel mosfet on resistance v in = 3.6v, csp package 75 m ? v in = 3.6v, mlp package 95 v in = 2.7v, mlp package 101 i lkgn n-channel leakage current v ds = 6v 1 a r dis discharge resistor for power-down sequence options 03 and 06 60 120 ? i limpk p-mos current limit 2.7v v in 4.2v, options 00 and 02 1150 1350 1600 ma 2.7v v in 5.5v, options 00 and 02 1050 1350 1600 2.7v v in 4.2v, options 03 and 06 1350 1550 1800 2.7v v in 5.5v, options 03 and 06 1250 1550 1800 t limit thermal shutdown 150 c t hyst thermal shutdown hysteresis 20 c frequency control f sw oscillator frequency 2.65 3.00 3.35 mhz f sync synchronization range 2.7 3.0 3.3 mhz d sync synchronization duty cycle 20 80 % continued on the following page?
? 2008 fairchild semiconductor corporation 6 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator electrical specifications (continued) v in = 3.6v, en = v in , vsel = v in , sync = gnd, vsel0(6) bit = 1, control2[4:3] = 00. t a = -40c to +85c, unless otherwise noted. typical values are at t a = 25c. circuit and components according to figure 1. symbol parameter conditions min. typ. max. units output regulation v out v out accuracy option 00 i out(dc) = 0, forced pwm, v out = 1.35v ?1.5 1.5 % 2.7v v in 5.5v, v out from 0.75 to 1.5375, i out(dc) = 0 to 800ma, forced pwm ?2 2 % 2.7v v in 5.5v, v out from 0.75 to 1.5375, i out(dc) = 0 to 800ma, pfm mode ?1.5 3.5 % option 02 i out(dc) = 0, forced pwm, v out = 1.20v ?1.5 1.5 % 2.7v v in 5.5v, v out from 0.75 to 1.4375, i out(dc) = 0 to 800ma, forced pwm ?2 2 % 2.7v v in 5.5v, v out from 0.75 to 1.4375, i out(dc) = 0 to 800ma, pfm mode ?1.5 3.5 % option 03 i out(dc) = 0, forced pwm, v out = 1.20v ?1.5 1.5 % 2.7v v in 5.5v, v out from 0.75 to 1.5375, i out(dc) = 0 to 1a, forced pwm ?2 2 % 2.7v v in 5.5v, v out from 0.75 to 1.5375, i out(dc) = 0 to 1a, pfm mode ?1.5 3.5 % option 06 i out(dc) = 0, forced pwm, v out = 1.800v ?1.5 1.5 % 2.7v v in 5.5v, v out from 1.185 to 1.975, i out(dc) = 0 to 1a, forced pwm ?2 2 % 2.7v v in 5.5v, v out from 1.185 to 1.975, i out(dc) = 0 to 1a, pfm mode ?1.5 3.5 % load out i v load regulation i out(dc) = 0 to 800ma, forced pwm ?0.5 %/a in out v v line regulation 2.7v v in 5.5v, i out(dc) = 300ma 0 %/v v ripple output ripple voltage pwm mode, v out = 1.35v 2.2 mv pp pfm mode, i out(dc) = 10ma 20 mv pp continued on the following page?
? 2008 fairchild semiconductor corporation 7 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator electrical specifications (continued) v in = 3.6v, en = v in , vsel = v in , sync = gnd, vsel0(6) bit = 1, control2[4:3] = 00. t a = -40c to +85c, unless otherwise noted. typical values are at t a = 25c. circuit and components according to figure 1. symbol parameter conditions min. typ. max. units 6-bit dac differential nonlinearity monotonicity assured by design 0.8 lsb timing i 2 c en en high to i 2 c start 250 s t v(l-h) v out low to high settling r load = 75 , transition from 1.0 to 1.5375v v out settled to within 2% of set point 7 s soft start t ss regulator enable to regulated v out option 06 r load > 5 , to v out = 1.8000v 170 210 s all other options r load > 5 , to v out = power-up default 140 180 s v slew soft-start v out slew rate (10) 18.75 v/ms note: 10. option 03 and 06 slew rates are 35.5v/ms during the first 16 s of soft start. ref 7-bit dac soft start fpwm en_reg clk 3 mhz osc i 2 c interface and logic en vsel sync sda scl sw q1 q2 pgnd pvin c out vout l out vout c in agnd avin modulator vin figure 4. block diagram
? 2008 fairchild semiconductor corporation 8 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator i 2 c timing specifications guaranteed by design. symbol parameter conditions min. typ. max. units f scl scl clock frequency standard mode 100 khz fast mode 400 khz high-speed mode, c b < 100pf 3400 khz high-speed mode, c b < 400pf 1700 khz t buf bus-free time between stop and start conditions standard mode 4.7 s fast mode 1.3 s t hd;sta start or repeated-start hold time standard mode 4 s fast mode 600 ns high-speed mode 160 ns t low scl low period standard mode 4.7 s fast mode 1.3 ns high-speed mode, c b < 100pf 160 ns high-speed mode, c b < 400pf 320 ns t high scl high period standard mode 4 s fast mode 600 ns high-speed mode, c b < 100pf 60 ns high-speed mode, c b < 400pf 120 ns t su;sta repeated-start setup time standard mode 4.7 s fast mode 600 ns high-speed mode 160 ns t su;dat data setup time standard mode 250 ns fast mode 100 ns high-speed mode 10 ns t hd;dat data hold time (7) standard mode 0 3.45 s fast mode 0 900 ns high-speed mode, c b < 100pf 0 70 ns high-speed mode, c b < 400pf 0 150 ns t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 ns high-speed mode, c b < 100pf 10 80 ns high-speed mode, c b < 400pf 20 160 ns t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 ns high-speed mode, c b < 100pf 10 40 ns high-speed mode, c b < 400pf 20 80 ns t rda t rcl1 sda rise time rise time of scl after a repeated start condition and after ack bit standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 ns high-speed mode, c b < 100pf 10 80 ns high-speed mode, c b < 400pf 20 160 ns t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 ns high-speed mode, c b < 100pf 10 80 ns high-speed mode, c b < 400pf 20 160 ns t su;sto stop condition setup time standard mode 4 s fast mode 600 ns high-speed mode 160 ns c b capacitive load for sda and scl 400 pf
? 2008 fairchild semiconductor corporation 9 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator timing diagrams start repeated start scl sda t f t hd;sta t low t r t hd;dat t high t su;dat t su;sta t hd;sto t buf start stop t hd;sta figure 5. i 2 c interface timing for fast and slow modes repeated start sclh sdah t fda t low t rcl1 t hd;dat t high t su;sto repeated start t rda t fcl t su;dat t rcl stop = mcs current source pull-up = r p resistor pull-up note a note a: first rising edge of sclh after repeated start and after each ack bit. t hd;sta t su;sta figure 6. i 2 c interface timing for high-speed mode
? 2008 fairchild semiconductor corporation 10 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics unless otherwise specified, auto-pwm/pfm, v in = 3.6v, t a = 25c, and recommended components as specified in table 1. efficiency 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 1101001000 i load output curre nt (ma) efficiency auto pwm/pfm forced pwm v in = 3.6v v out = 1.05v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 1 10 10 0 100 0 i load output curre nt (ma) efficiency auto pwm/pfm forced pwm v in = 3.6v v out = 1.35v figure 7. efficiency vs. load at v out = 1.05v figure 8. efficiency vs. load at v out = 1.35v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 1101001000 i load output curre nt (ma) efficiency auto pwm/pfm forced pwm v in = 3.6v v out = 1.5v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 i load output current (ma) efficiency auto pwm/pfm forced pwm v in = 3.6v v out =1.8v figure 9. efficiency vs. load at v out = 1.50v figure 10. efficiency vs. load at v out = 1.80v
? 2008 fairchild semiconductor corporation 11 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics unless otherwise specified, auto-pwm/pfm, v in = 3.6v, t a = 25c, and recommended components as specified in table 1. 1.048 1.050 1.052 1.054 1.056 1.058 1.060 1.062 1.064 1 10 100 1000 i load output current (ma) vout (v) auto pwm/pfm forced pwm 1.348 1.350 1.352 1.354 1.356 1.358 1.360 1.362 1.364 1 10 100 1000 i load output current (ma) vout (v) auto pwm/pfm forced pwm figure 11. load regulation at v out = 1.05v figure 12. load regulation at v out = 1.35v 1.798 1.800 1.802 1.804 1.806 1.808 1.810 1.812 1.814 1.816 1 10 100 1000 i load output current (m a) v out (v) auto pwm/pfm forced pwm -0.30% -0.25% -0.20% -0.15% -0.10% -0.05% 0.00% 0.05% 0.10% -40-20 0 20406080 temperature (c) output voltage (v) vin = 2.7v vin = 3.6v vin = 5.5v figure 13. load regulation at v out = 1.80v figure 14. % v out shift vs. temperature (normalized) 30 35 40 45 50 55 60 65 70 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vin input voltage (v) quiescent current ( a) vsel = 1.8v vsel = 0v 1.0 2.0 3.0 4.0 5.0 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in input voltage (v) shutdown current (a) vsel = 1.8v vsel = 0v figure 15. quiescent current, i load = 0, en = 1.8v figure 16. shutdown current, i load = 0, en = 0
? 2008 fairchild semiconductor corporation 12 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics (continued) unless otherwise specified, v in = 3.6v, v out = 1.35v, and load step t r = t f < 100ns. load transient response figure 17. 50ma to 400ma to 50ma, forced pwm figure 18. 50ma to 400ma to 50ma, auto pwm/pfm figure 19. 400ma to 750ma to 400ma, auto pwm/pfm figure 20. 0ma to 125ma to 0ma, auto pwm/pfm
? 2008 fairchild semiconductor corporation 13 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics (continued) unless otherwise specified, v in = 3.6v. vsel transitions figure 21. single-step, r load = 6.2 ? figure 22. single-step, r load = 6.2 ? figure 23. single-step, r load = 50 ? figure 24. single-step, r load = 50 ?
? 2008 fairchild semiconductor corporation 14 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics (continued) unless otherwise specified, v in = 3.6v. vsel transitions figure 25. single-step from forced pwm (mode1=0), r load = 50 ? figure 26. single-step, r load = 6.2 ? figure 27. single?step from auto pwm/pfm (mode1=1), r load = 50 ? figure 28. multi-step, controlled dac step (9.6mv/s) def_slew 6 (110), 800ma load vsel v out i l
? 2008 fairchild semiconductor corporation 15 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics (continued) r load is switched with n-channel mosfet from vout to gnd. v in = 3.6v, initial v out = 1.35v, initial i load = 0ma. short circuit and over-current fault response figure 29. metallic short applied at vout figure 30. metallic short applied at vout figure 31. r load = 660m ? figure 32. r load = 660m ?
? 2008 fairchild semiconductor corporation 16 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator typical performance characteristics (continued) unless otherwise specified, v in = 3.6v. figure 33. sw-node jitter (infinite persistence), i load = 200ma figure 34. sw-node jitter, external synchronization (infinite persistence), i load = 200ma (10) - 10 20 30 40 50 60 70 0.1 1.0 10.0 100.0 1,000.0 frequency (khz) psrr attenuation (db) iout=500ma iout=150ma iout=20ma figure 35. soft start, r load = 50 figure 36. v in ripple rejection (psrr)
? 2008 fairchild semiconductor corporation 17 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator circuit description overview the fan5355 is a synchronous buck regulator that typically operates at 3mhz with moderate to heavy load currents. at light load currents, the converter operates in power-saving pfm mode. the regulator automatically transitions between fixed-frequency pwm and variable-frequency pfm mode to maintain the highest possible efficiency over the full range of load current. the fan5355 uses a very fast non-linear control architecture to achieve excellent transient response with minimum-sized external components. the fan5355 integrates an i 2 c-compatible interface, allowing transfers up to 3.4mbps. this communication interface can be used to: 1. dynamically re-program the output voltage in 12.5mv increments. 2. reprogram the mode of operation to enable or disable pfm mode. 3. control voltage transition slew rate. 4. control the frequency of operation by synchronizing to an external clock. 5. enable / disable the regulator. for more details, refer to the i 2 c interface and register description sections. output voltage programming option (11) v out equation 00, 02, 03 mv 5 . 12 n 75 . 0 v vsel out ? + = (1) 06 mv 5 . 12 n 1875 . 1 v vsel out ? + = (2) where n vsel is the decimal value of the setting of the vsel register that controls v out . note: 11. option 02 maximum voltage is 1.4375v (see table 3) . power-up, en, and soft-start all internal circuits remain de-biased and the ic is in a very low quiescent-current state until the following are true: 1. v in is above its rising uvlo threshold, and 2. en is high. at that point, the ic begins a soft-start cycle, its i 2 c interface is enabled, and its registers are loaded with their default values. during the initial soft start, v out ramps linearly to the set point programmed in the vsel register selected by the vsel pin. the soft start features a fixed output-voltage slew rate of 18.75v/ms and achieves regulation approximately 90 s after en rises. pfm mode is enabled during soft start until the output is in regulation, regardless of the mode bit settings. this allows the regulator to st art into a partially charged output without discharging it; in other words, the regulator does not allow current to flow from the load back to the battery. as soon as the output has reached its set point, the control forces pwm mode for about 85 s to allow all internal control circuits to calibrate. symbol description value ( s) t ssdly time from en to start of soft-start ramp 75 t reg v out ramp start to regulation opt 03, 06 16 +(vsel?0.7) x 53 opt 00, 02 (vsel?0.1) x 53 t pok pwrok (control2[5]) rising from end of t reg and regulator stays in pwm mode during this time 10 table 2. soft-start timing (see figure 37) figure 37. soft-start timing
? 2008 fairchild semiconductor corporation 18 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator table 3. vsel vs. vout dec binary hex 00, 03 02 06 0 000000 00 0.7500 0.7500 1.1875 1 000001 01 0.7625 0.7625 1.2000 2 000010 02 0.7750 0.7750 1.2125 3 000011 03 0.7875 0.7875 1.2250 4 000100 04 0.8000 0.8000 1.2375 5 000101 05 0.8125 0.8125 1.2500 6 000110 06 0.8250 0.8250 1.2625 7 000111 07 0.8375 0.8375 1.2750 8 001000 08 0.8500 0.8500 1.2875 9 001001 09 0.8625 0.8625 1.3000 10 001010 0a 0.8750 0.8750 1.3125 11 001011 0b 0.8875 0.8875 1.3250 12 001100 0c 0.9000 0.9000 1.3375 13 001101 0d 0.9125 0.9125 1.3500 14 001110 0e 0.9250 0.9250 1.3625 15 001111 0f 0.9375 0.9375 1.3750 16 010000 10 0.9500 0.9500 1.3875 17 010001 11 0.9625 0.9625 1.4000 18 010010 12 0.9750 0.9750 1.4125 19 010011 13 0.9875 0.9875 1.4250 20 010100 14 1.0000 1.0000 1.4375 21 010101 15 1.0125 1.0125 1.4500 22 010110 16 1.0250 1.0250 1.4625 23 010111 17 1.0375 1.0375 1.4750 24 011000 18 1.0500 1.0500 1.4875 25 011001 19 1.0625 1.0625 1.5000 26 011010 1a 1.0750 1.0750 1.5125 27 011011 1b 1.0875 1.0875 1.5250 28 011100 1c 1.1000 1.1000 1.5375 29 011101 1d 1.1125 1.1125 1.5500 30 011110 1e 1.1250 1.1250 1.5625 31 011111 1f 1.1375 1.1375 1.5750 32 100000 20 1.1500 1.1500 1.5875 33 100001 21 1.1625 1.1625 1.6000 34 100010 22 1.1750 1.1750 1.6125 35 100011 23 1.1875 1.1875 1.6250 36 100100 24 1.2000 1.2000 1.6375 37 100101 25 1.2125 1.2125 1.6500 38 100110 26 1.2250 1.2250 1.6625 39 100111 27 1.2375 1.2375 1.6750 40 101000 28 1.2500 1.2500 1.6875 41 101001 29 1.2625 1.2625 1.7000 42 101010 2a 1.2750 1.2750 1.7125 43 101011 2b 1.2875 1.2875 1.7250 44 101100 2c 1.3000 1.3000 1.7375 45 101101 2d 1.3125 1.3125 1.7500 46 101110 2e 1.3250 1.3250 1.7625 47 101111 2f 1.3375 1.3375 1.7750 48 110000 30 1.3500 1.3500 1.7875 49 110001 31 1.3625 1.3625 1.8000 50 110010 32 1.3750 1.3750 1.8125 51 110011 33 1.3875 1.3875 1.8250 52 110100 34 1.4000 1.4000 1.8375 53 110101 35 1.4125 1.4125 1.8500 54 110110 36 1.4250 1.4250 1.8625 55 110111 37 1.4375 1.4375 1.8750 56 111000 38 1.4500 1.4375 1.8875 57 111001 39 1.4625 1.4375 1.9000 58 111010 3a 1.4750 1.4375 1.9125 59 111011 3b 1.4875 1.4375 1.9250 60 111100 3c 1.5000 1.4375 1.9375 61 111101 3d 1.5125 1.4375 1.9500 62 111110 3e 1.5250 1.4375 1.9625 63 111111 3f 1.5375 1.4375 1.9750 vsel value vout software enable the en_dcdc bit, vselx[7] can be used to enable the regulator in conjunction with the en pin. setting en_dcdc with en high begins the soft-start sequence described above. en_dcdc bit en pin i 2 c regulator 0 0 off off 1 1 on on 1 0 off off 0 1 on off table 4. en_dcdc behavior light-load (pfm) operation the fan5355 offers a low-ripple, single-pulse pfm mode to save power and improve efficiency when the load current is very low. pfm operation features: ? smooth transitions between pfm and pwm modes ? single-pulse operation for low ripple ? predictable pfm entry and exit currents. pfm begins after the inductor current has become discontinuous, crossing zero during the pwm cycle in 32 consecutive cycles. pfm exit occurs when discontinuous current mode (dcm) operation cannot supply sufficient current to maintain regulation. during pfm mode, the inductor current ripple is about 40% higher than in pwm mode. the load current required to exit pfm mode is thereby about 20% higher than the load current required to enter pfm mode, providing sufficient hysteresis to prevent ?mode chatter.? while pwm ripple voltage is typically less than 4mv pp , pfm ripple voltage can be up to 30mv pp during very light load. to prevent significant undershoot when a load transient occurs, the initial dc set point for the regulator in pfm mode is set 10mv higher than in pwm mode. this offset decays to about 5mv after the regulator has been in pfm mode for ~100 s. the maximum instantaneous voltage in pfm is 30mv above the set point. pfm mode can be disabled by writ ing to the mode control bits: control1[3:0] ( see table 10 for details ). some vendors provide both ?light pfm? (lpfm) and ?fast pfm? (fpfm) modes, while the fan5355 provides only one pfm mode. the fan5355?s single pfm mode features the fast transient recovery of fpfm, but does this with the low quiescent current consumption similar to lpfm mode.
? 2008 fairchild semiconductor corporation 19 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator switching-frequency control and synchronization the nominal internal oscillator frequency is 3mhz. the regulator runs at its internal clock frequency until these conditions are met: 1. en_sync bit, control1[5], is set; and 2. a valid frequency appears on the sync pin. control2 f sync valid pll_mult f sync divider min. typ. max. 00 1 1.80 3.00 4.00 01 2 0.90 1.50 2.00 10 3 0.60 1.00 1.33 11 4 0.45 0.75 1.00 table 5. sync frequency validation for f osc(internal) =3.0mhz if the en_sync is set and sync fails validation, the regulator continues to run at its internal oscillator frequency. the regulator is functional if f sync is valid, as defined in table 5, but its performance is compromised if f sync is outside the f sync window in the electrical specifications. when control1[3:2] = 00 and the vsel line is low, the converter operates according to the mode0 bit, control1[0], with synchronization disabled regardless of the state of the en_sync and hw_nsw bits. output voltage transitions the ic regulates v out to one of two set point voltages, as determined by the vsel pin and the hw_nsw bit. vsel pin hw_nsw bit v out set point pfm 0 1 vsel0 allowed 1 1 vsel1 per mode1 x 0 vsel1 per mode1 table 6. v out set point and mode control mode_ctrl, control1[3:2] = 00 if hw_nsw = 0, v out transitions are initiated through the following sequence: 1. write the new setpoint in vsel1. 2. write desired transition rate in defslew, control2[2:0], and set the go bit in control2[7]. if hw_nsw = 1, v out transitions are initiated either by changing the state of the vsel pin or by writing to the vsel register selected by the vsel pin. positive transitions when transitioning to a higher v out , the regulator can perform the transition using multi-step or single-step mode. multi-step mode: applies to options 03 and 06 only. the internal dac is stepped at a rate defined by defslew, control2[2:0], ranging from 000 to 110. this mode minimizes the current required to charge c out and thereby minimizes the current drain from the battery when transitioning. the pwrok bit, control2[5], remains low until about 1.5 s after the dac completes its ramp. vlow vhigh vsel vout pwrok t pok(l-h) figure 38. multi-step v out transition single-step mode: used if defslew, control2[2:0] = 111. the internal dac is immediately set to the higher voltage and the regulator performs the transition as quickly as its current-limit circuit allows, while avoiding excessive overshoot. figure 39 shows single-step transition timing. t v(l-h) is the time it takes the regulator to settle to within 2% of the new set point and is typically 7 s for a full-range transition (from 000000 to 111111). the pwrok bit, control2[5], goes low until the transition is complete and v out settled. this typically occurs ~2 s after t v(l-h) . it is good practice to reduce the load current before making positive vsel transitions. this reduces the time required to make positive load transitions and avoids current-limit-induced overshoot. t v(l-h) vlow vhigh 98% vhigh vsel vout pwrok t pok(l-h) figure 39. single-step v out transition all positive v out transitions inhibit pfm until the transition is complete, which occurs at the end of t pok(l-h) .
? 2008 fairchild semiconductor corporation 20 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator negative transitions when moving from vsel=1 to vsel=0, the regulator enters pfm mode, regardless of the condition of the sync pin or mode bits, and remains in pfm until the transition is completed. reverse current through the inductor is blocked, and the pfm minimum frequency control inhibited, until the new set point is reached, at which time the regulator resumes control using the mode established by mode_ctrl. the transition time from v high to v low is controlled by the load current and output capacitance as: load low high out ) l h ( v i v v c t ? ? = ? (3) vhigh vsel vout pwrok t pok(l-h) t v(l-h) vlow figure 40. negative v out transition protection features current limit / auto-restart the regulator includes cycle-by-cycle current limiting, which prevents the instantaneous inductor current from exceeding the current-limit threshold. the ic enters ?fault? mode after sustained over-current. if current limit is asserted for more than 32 consecutive cycles (about 20 s), the ic returns to shut-down state and remains in that condition for ~80 s. after that time, the regulator attempts to restart with a normal soft-start cycle. if the fault has not cleared, it shuts down ~10 s later. if the fault is a short circuit, the initial current limit is ~30% of the normal current limit, which produces a very small drain on the system power source. thermal protection when the junction temperature of the ic exceeds 150c, the device turns off all output mosfets and remains in a low quiescent-current state until the die cools to 130c before commencing a normal soft-start cycle. under-voltage lockout (uvlo) the ic turns off all mosfets and remains in a very low quiescent-current state until v in rises above the uvlo threshold. i 2 c interface the fan5355?s serial interface is compatible with standard, fast, and hs mode i 2 c bus specifications. the fan5355?s scl line is an input and its sda line is a bi-directional open- drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. sda and scl are normally pulled up to a system i/o power supply (vccio), as shown in figure 1. if the i 2 c interface is not used, sda and scl should be tied to avin to minimize quiescent current consumption. addressing fan5355 has four user-accessible registers: address 7 6 5 4 3 2 1 0 vsel0 0 0 0 0 0 0 0 0 vsel1 0 0 0 0 0 0 0 1 control1 0 0 0 0 0 0 1 0 control2 0 0 0 0 0 0 1 1 table 7. i 2 c register addresses slave address in table 8, a1 and a0 are according to the ordering information table on page 2. 7 6 5 4 3 2 1 0 1 0 0 1 0 a1 a0 w r/ table 8. i 2 c slave address bus timing as shown in figure 41, data is normally transferred when scl is low. data is clocked in on the rising edge of scl. typically, data transitions shortly at or after the falling edge of scl to allow ample time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 41. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a ?start? condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in figure 42.
? 2008 fairchild semiconductor corporation 21 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator scl t hd;sta sda slave address ms bit figure 42. start bit a transaction ends with a ?stop? condition, which is defined as sda transitioning from 0 to 1 with scl high, as shown in figure 43. scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 43. stop bit during a read from the fan 5355 (figure 46), the master issues a ?repeated start? after sending the register address and before resending the slave address. the ?repeated start? is a 1 to 0 transition on sda while scl is high, as shown in figure 44. high-speed (hs) mode the protocols for high-speed (hs), low-speed (ls), and fast-speed (fs) modes are identical, except the bus speed for hs mode is 3.4mhz. hs mode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is sent in fs mode (less than 400khz clock) and slaves do not ack this transmission. the master then generates a r epeated-start condition (figure 44) that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs-mode clock rate and timing. the bus remains in hs mode until a stop bit (figure 43) is sent by the master. while in hs mode, packets are separated by repeated-start conditions (figure 44). scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 44. repeated-start timing read and write transactions the following figures outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as master drives bus and slave drives bus . all addresses and data are msb first. symbol definition s start, see figure 42 . a ack. the slave drives sda to 0 to acknowledge the preceding packet. a nack. the slave sends a 1 to nack the preceding packet. r repeated start, see figure 44 . p stop, see figure 43 . table 9. i 2 c bit definitions for figure 45 - figure 46 s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 45. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 46. read transaction
? 2008 fairchild semiconductor corporation 22 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator register descriptions default values each option of the fan5355 (see ordering information on page 2) has different default values for the some of the register bits. table 10 defines both the default val ues and the bit?s type (as defined in t able 11) for each available option. vsel0 option 7 6 5 4 3 2 1 0 v out 00 1 1 0 1 1 0 0 0 1.05 02 1 1 0 1 1 0 0 0 1.05 03 1 1 0 1 0 1 0 0 1.00 06 1 1 1 1 0 0 0 1 1.80 vsel1 option 7 6 5 4 3 2 1 0 v out 00 1 1 1 1 0 0 0 0 1.35 02 1 1 1 0 0 1 0 0 1.20 03 1 1 1 0 0 1 0 0 1.20 06 1 1 1 1 0 0 0 1 1.80 control1 option 7 6 5 4 3 2 1 0 00, 02 1 0 0 1 0 0 0 0 03, 06 1 0 0 1 0 0 0 0 control2 option 7 6 5 4 3 2 1 0 00, 02 0 0 1 0 0 1 1 1 03, 06 0 0 1 0 0 1 1 1 table 10. default values and bit types for vsel and control registers # active bit. changing this bit changes the behavior of the converter, as described below. # disabled. converter logic ignores changes made to this bit. bit can be written to and read-back. # read-only . writing to this bit through i 2 c does not change the read-back value, nor does it change converter behavior. table 11. bit-type definitions for table 10
? 2008 fairchild semiconductor corporation 23 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator bit definitions the following table defines the operation of each register bit. superscript characters define the default state for each option . superscripts 0,2,3,6 signify the default values for options 00, 02, 03, and 06, respectively. a signifies the default for all options. bit name value description vsel0 register address: 00 7 en_dcdc 0 device in shutdown regardless of the state of the en pin. this bit is mirrored in vsel1. a write to bit 7 in either register establishes the en_dcdc value. 1 a device enabled when en pin is high, disabled when en is low. 6 reserved 1 5:0 dac[5:0] table 10 6-bit dac value to set v out . vsel1 register address: 01 7 en_dcdc 0 device in shutdown regardless of the state of the en pin. this bit is mirrored in vsel0. a write to bit 7 in either register establishes the en_dcdc value. 1 a device enabled when en pin is high, disabled when en is low. 6 reserved 1 5:0 dac[5:0] table 10 6-bit dac value to set v out . control1 register address: 02 7:6 reserved 10 a vendor id bits. writing to these bits has no effect on regulator operation. these bits can be used to distinguish between vendors via i 2 c. 5 en_sync 0 a disables external signal on sync from affecting the regulator. 1 when a valid frequency is detected on sync, the regulator synchronizes to it and pfm is disabled, except when mode = 00, vsel pin = low, and hw_nsw = 1. 4 hw_nsw 0 v out is controlled by vsel1. voltage transitions occur by writing to the vsel1, then setting the go bit. 1 a v out is programmed by the vsel pin. v out = vsel1 when vsel is high, and vsel0 when vsel is low. 3:2 mode_ctrl 00 a operation follows mode0, mode1. 01 pfm with automatic transitions to pwm, regardless of vsel. 10 pfm disabled (forced pwm), regardless of vsel. 11 unused. 1 mode1 0 a pfm disabled (forced pwm) when regulator output is controlled by vsel1. 1 pfm with automatic transitions to pwm when regulator output is controlled by vsel1. 0 mode0 0 a pfm with automatic transitions to pwm when vsel is low. c hanging this bit has no effect on the operation of the regulator. 1 control2 register address: 03 7 go 0 a this bit has no effect when hw_nsw = 1. 1 starts a v out transition if hw_nsw = 0. this bit must be written by the external master to 1 for the next v out transition to start, even if its value might have already been 1 from the last v out transition. 6 output_ discharge 0 a when the regulator is disabled, v out is not discharged. 1 when the regulator is disabled, v out discharges through an internal pull down. 5 pwrok (read only) 0 v out is not in regulation or is in current limit. 1 v out is in regulation. 4:3 pll_mult 00 a f sw = f sync when synchronization is enabled. 01 f sw = 2 x f sync when synchronization is enabled. 10 f sw = 3 x f sync when synchronization is enabled. 11 f sw = 4 x f sync when synchronization is enabled. 2:0 defslew 000 v out slews at 0.15mv/ s during positive v out transitions. 001 v out slews at 0.30mv/ s during positive v out transitions. 010 v out slews at 0.60mv/ s during positive v out transitions. 011 v out slews at 1.20mv/ s during positive v out transitions. 100 v out slews at 2.40mv/ s during positive v out transitions. 101 v out slews at 4.80mv/ s during positive v out transitions. 110 v out slews at 9.60mv/ s during positive v out transitions. 111 a positive v out transitions use single-step mode (see figure 39) .
? 2008 fairchild semiconductor corporation 24 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator physical dimensions a1 e 0.625 0.539 seating plane 0.06 c 12 x ?0.315 +/- .025 top view bottom view (?0.35) solder mask opening (?0.25) cu pad recommended land pattern (nsmd) ball a1 index area 0.03 c 0.05 c d 2x (y)+/-.018 (x)+/-.018 b a d 0.2500.025 c 1 2 a b c 0.03 c 2x 0.005 cab 0.50 0.50 0.50 0.50 1.00 3 d 0.3320.018 b. dimensions are in millimeters. c. dimensions and tolerances per a. no jedec registration applies asme y14.5m, 1994 d datum c, the seating plane, is defined by the spherical crowns of the balls. for dimensions d, e, x, and y see product datasheet. f. ball composition: sn95.5ag3.9cu0.6 sac405 alloy g. drawing filename: mkt-uc012aarev2 f side views figure 47. 12-bump wlcsp, 0.5mm pitch product-specific dimensions product d e x y fan5355uc 2.210 +/-0.040 1.440 +/-0.040 0.220 0.355 package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation 25 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator physical dimensions b. dimensions are in millimeters. c. dimensions and tolerances per mlp10arevb a. conforms to jedec registration mo-229, variation weed-5 except where noted asme y14.5m, 1994 0.10 cab 0.05 c top view bottom view recommended land pattern 0.10 c 0.08 c b a c 3.0 3.0 0. 05 0. 00 0.10 c 2x 2x 0.8 max side view seating plane 0.10 c 0.5 2.0 (0.20) 1 5 6 10 pin #1 ident 2.40 1.40 (3.00 0.10 ) 0.30 0.20 0.55 0.10 e e. not compliant (3.00 0.10 ) (0.38) 6 10 15 2.25 3. 10 0.23 0.55 2.40 2. 00 1. 55 0.02 2.00 0.50 0.25 0.78 2. 33 d d. land pattern dimensio ns are no minal reference values only figure 48. 10-pin, 3x3mm molded leadless package (mlp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation 26 www.fairchildsemi.com fan5355 ? rev. 1.0.6 fan5355 ? 1a / 0.8a, 3mhz digitally programmable regulator

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